module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);

    wire		cout2;
    wire		cout1;
    reg			cout0;
    reg	[15:0]	sum2;
    reg	[15:0]	sum1;
    reg	[15:0]	sum0;
    
    always @(*) begin
       case (cout0)
           1'b0:	sum = {sum1, sum0};
           1'b1:	sum = {sum2, sum0};
       endcase
    end
    
    add16 u_add16_0(
        .a(a[15:0]),
        .b(b[15:0]),
        .cin(0),
        .sum(sum0),
        .cout(cout0)
    );
    
    add16 u_add16_1(
        .a(a[31:16]),
        .b(b[31:16]),
        .cin(0),
        .sum(sum1),
        .cout(cout1)
    );
    
    add16 u_add16_2(
        .a(a[31:16]),
        .b(b[31:16]),
        .cin(1),
        .sum(sum2),
        .cout(cout2)
    );
    
endmodule
